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If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers.

The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier OTA design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

Currently, we have high-capacity technology of analog and digital electronic devices due to the micro-components that are increasingly becoming smaller in scale. In fact, in , Gordon E. Unfortunately, often this knowledge is taught with specialized complex and expensive software, which is sometimes not readily available in many universities around the world.

Analog and digital integrated circuit design has emphasized a good understanding of analog and digital electronic circuits to model, simplify, analyze, and simulate microelectronic devices before developing layouts and sending devices to IC fabrication foundry consortiums. Microelectronics courses and specialized workshops and webinars teach conceptual design where the following concepts are emphasized. IC design is important in device development for microelectronics engineering innovation and is embedded into the design flow which may have continuous iterations to optimize designs by decision refinements.

In the process of CMOS microelectronics conceptual design [ 5 , 6 , 7 ], the electrical device specification requires active and passive models for creating, verifying, and determining the robustness of the design. This process involves the selection of a conceptual circuit, the analysis of the selected circuit, the possibility of a modification to the circuit, and the verification of the circuit solution. The physical electronics design process [ 8 , 9 , 10 ] consists of representing the electrical device in a 2D layout consisting of many different geometrical rectangles at various levels layers.

This layout is then used to implement a 3D integrated circuit during the fabrication process. The device conceptual model follows a process to obtain a layout. This process includes [ 3 , 4 ]:. This process is depicted in the flow diagram shown below in Figure 2. Once the first approach to design is terminated, the process continues with design testing which consists of coordinating, planning, and implementing the measurement of the integrated circuit performance. Several tests are available, e.

Additional testing could include device testing performed at the wafer level or package level and detailed testing that removes the influence of measurement system in the device performance. Several methodologies have been developed for CMOS device design and testing but most of them are very specific to the final prototype or experimental application [ 11 , 12 , 13 , 14 , 15 , 16 , 17 ].

The Excel methods analyzed in this study focus on providing didactic instruction in microelectronics for undergraduate and graduate students. Therefore, it seeks to focus learning by referring to world trends in conducting open science, providing the social appropriation of knowledge.

The forefront is didactic management whose central axis is the catalyst of open innovation processes that have proven to be very successful disruptive models in open laboratories, universities, research centers, industry, and government for the development of emerging economies and public policies [ 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ].

In addition, several contributions stand out:. The Excel methods discussed here focus on microelectronics education for undergraduate and graduate students. Furthermore, several contributions are emphasized:. This manuscript is organized as follows. Section 2 briefly describes device modeling to represent transistors using first principle equations that predict their behavior in different regimes and operating conditions.

Section 3 provides the basic MOSFET modeling equations, starting with the threshold voltage calculations, the transconductance equations for the ohmic sub-saturation , active saturation , and subthreshold conditions, both for long channel and short channel devices. Section 4 describes the Excel methods that students use to develop their first cut approximations in conceptual designs of CMOS devices and before testing schematic simulations and layouts.

This section also discusses resistance, capacitance, and differential amplifier conceptual designs as specific examples to apply the Excel methods. Section 5 discusses the Excel methods applied for complete amplifier design. Here the cascode amplifier and the OTA Operational Transconductance Amplifier are used as examples of how students use the basic two-dimensional Excel methodology to solve CMOS microelectronic conceptual design devices.

Section 6 illustrates a complete case study, developed by students and wrapped up by their instructor, of a low-power high-gain operational amplifier for biomedical applications. Finally, Section 7 wraps up the paper with illustrative conclusions about how these Excel methods have provided extraordinary insights to undergraduate students in their effort to consolidate a good understanding of microelectronics conceptual integrated circuit IC design.

The process of device modeling consists of representing the electrical properties of devices using mathematical equations, circuits, graphs, correlations, and energy conservation laws. Models allow predictions and validation of circuit performance with uncertainties coming from no-idealities and non-linear behaviors in electronic components.

The final goals are to simplify the cause—effect relationships allowing the engineer to understand and consider decisions that increase performance in the circuit. Analog integrated circuits in microelectronic conceptual design are developed using a non-hierarchical structure where the use of repeated blocks is only possible in few devices, and therefore the design process is complex and challenging.

To handle this, design engineers use hierarchy whenever possible, use good organization techniques, efficiently document the design, provide reasonable and reliable assumptions and simplifications, and eventually validate the conceptual designs using simulation experiments. Assumptions and simplifications are used to emphasize the essential characteristics by neglecting the non-dominant effects in the design. The challenge of teaching microelectronics is to develop an insight into the design process without requiring specialized professional software which is not readily available in many universities around the world.

Figure 3 shows the microelectronics design process, on the left side, with the insight given on the right side, using Excel methods and other simulation techniques which are readily available to universities. The CMOS microelectronics design process and the insight provided by the Excel methods in the quest to teach microelectronics design with simple tools.

Analog integrated circuit design and device evaluation have reached a level of maturity in established applications such as digital to analog and analog to digital conversion systems, front end signal conditioning devices, instrumentation channel devices, bandgap reference sources, DC to DC power conversion drives, and other important microelectronic circuits [ 3 ]. Finally, analog circuit conceptual designs have significant applications in devices where speed and power have an overwhelming advantage over digital devices.

This paper reviews the long and short channel models for CMOS devices and further application of long channel equations using Excel methods for first cut approximations before computer simulations and layout development. Those approximation models can be found in many CMOS microelectronics specialized textbooks [ 3 , 4 , 7 , 27 , 28 , 29 ] and they are summarized here for completeness in this discussion.

The evaluation of threshold voltage, V T , is fundamental in the development of CMOS microtechnology because gives the necessary condition for allowing operation of the transistors in the right zone. To consider velocity saturation and effective mobility in short channel MOSFETs adjustments are made in the model equations presented above. This is particularly important in the saturated and ohmic regions of operation. The two most important parameters are g m , transconductance gain, and g d s , output conductance of the device which provides its output resistance [ 3 , 4 ].

The equations for those parameters are described as follows. These parameters are evaluated at the quiescent Q point where the device operates and the small-signal ignites. The most important parasitic elements of the MOSFET are the capacitances due to the inherent field-effect operation of this transistor. The oxide and p-n junction capacitances are responsible for limitations of the frequency response which generates poles and zeros which are frequently analyzed to determine the stability of the device and the dominant bandwidth of the system.

Three capacitances are considered in the conceptual design modeling:. In microelectronic conceptual design, the passive components provide additional versatility in the consolidation and refinement of many integrated circuits that require compensation, parasitic element adjustment, antenna integration, and other possible maneuvers.

For the conceptual modeling using the Excel methodologies, this paper considers only resistor and capacitor implementations. To implement resistances, Table 3 shows the values for sheet and contact resistances in the C5 ON-SEMI process [ 15 ] described by wafer runs from the corresponding foundry.

Resistance process parameters for CMOS 0. Parameters from table IV are very important in the compensation of analog integrated circuits that are used in instrumentation channels for processing signals coming from sensors and transducers.

Capacitance process parameters for CMOS 0. The equations to implement passive components are given as follows. Now that the model equations have been presented, the following sections will discuss the methodology used to describe the conceptual model for the CMOS microelectronic circuit. Conceptual design involves the use of parameters and constants to compute and size values of components and electrical variables [ 16 , 17 ].

However, sometimes the number of specifications given is larger than the number of degrees of freedom available to the designer trying to comply and fulfill them [ 3 , 4 , 27 , 28 , 29 ]. Therefore, in the design process, a series of decision points is necessary to iterate the processing flow before obtaining the final solution. Several trials are necessary and sometimes, intermediate simulations are required to analyze different alternative solutions.

In this case, the use of Excel methods is convenient while advancing in the design process. There are three sorts of recommended methods:. In the single straight processing, the method proceeds in a horizontal fashion with the CMOS technology parameters in the first block of columns. Then, the processing flow continues sequentially, column by column, until the final desired calculation values are obtained. If several conditions are considered, then a row repetition is developed accordingly.

The artwork was developed once the Excel method was used to calculate the number of sheets or squares required by the conceptual design. In the tabular processing, the method proceeds as usual, in a horizontal fashion to evaluate the design instance with the CMOS technology parameters in the first block of columns.

However, this evaluation is repeated for a multiple number of instances while varying one or two specifications or parameters. Then, the processing flow continues sequentially, row by row, until the final desired instance is terminated. Each instance considered will be evaluated over a single row. Figure 7 and Figure 8 show tabular processing to design capacitances using poly-poly-2 CMOS nm technology.

Figure 5 starts with the value of the capacitance and ends up with squared plates in Poly-Poly to design the capacitance. The artwork was also developed once the Excel methodology was used to evaluate the conceptual design. Capacitors from Figure 8 and Figure 9 are used for operational transconductance amplifier OTA compensation later in this paper. Tabular method to design CMOS capacitances. This Excel goes from capacitance value to X-Y dimensions.

This Excel sheet goes from X-Y dimensions to capacitance value. In two-dimensional processing, the method proceeds with the horizontal first row having the specifications and CMOS technology parameters of the conceptual design. Each row will define a step in the processing design flow such that the Excel will progress down and away from the first cell of the spreadsheet.

The evaluations are arranged such that intermediate calculations follow a slope down from the early decisions all the way to the last decision. Usually, an iterative process is necessary to comply with two or three specifications with a single degree of freedom. Figure 11 illustrates the Excel method to develop the conceptual design for a CMOS differential amplifier. The method illustrates the step-by-step evaluation and decision-making process downward, and the CMOS technology specifications are shown rightwards as shown in Figure The CMOS Technology characteristics flow horizontally to the right and the CMOS design equations, from 5 to 10 , flow downwards illustrating the step-by-by step procedure.

However, if a particular spec does not convince the design engineer, the processing flow can be stopped, and a recalculation with a different spec or different decision making is readily possible at every row. Two-dimensional processing method to design a differential amplifier. From the initial cell top-left , the conceptual design progress downward, step by step, and to the right to size each transistor.

Figure 12 shows the schematic from Electric-VLSI of a differential amplifier using results from the Excel two-dimensional method. Once this schematic circuit model is tested, the next step is developing the layout. Differential amplifiers are the core of every instrumentation amplifier and their layout must be considered very carefully. Figure 13 shows the strategy recommended by J. Baker [ 4 ] to develop a common centroid layout. Common centroid layout recommended for big matched differential pair transistors [ 3 , 4 ].

The Excel methodologies shown previously can be applied to develop conceptual designs of complete functional blocks such as a cascode amplifier with its bias circuit, and a two-stage operational transconductance amplifiers OTA. The OTA amplifier includes a compensation capacitance which is necessary to ensure stability and reliable operation for the required frequency response. Even though the following design examples are not very specialized, the literature shows many examples of more specialized conceptual designs where microelectronic design has been extended [ 30 , 31 , 32 , 33 ].

The design flow that students must follow to perform the conceptual design of the microelectronic device is given as follows:. The cascode amplifier obtains a higher gain and output resistance than the traditional inverting amplifier stages. Typical design parameters are slew rate SR , output swing, and power dissipation for a simple cascode stage. Figure 15 illustrates the Excel method to develop the conceptual design for a cascode amplifier. As mentioned before, the method illustrates the step-by-step evaluation and decision-making process downwards and the processing flow goes rightwards.

Again, the CMOS Technology characteristics and specifications flow horizontally to the right and the CMOS design equations, from 5 to 10 , flow downwards illustrating the step-by-by step procedure. The bias circuit was implemented and evaluated in a separate analysis using the guidelines from J.

Baker [ 4 ]. Once this schematic circuit model is tested, the next step is to develop the layout. The layout is developed using Electric-VLSI and includes both the bias circuit and the three stacked transistors as shown previously in Figure This layout shows the transistors in horizontal layouts where the lower two levels include N-type transistors, and the upper level includes the P-type transistors which appear in the circuit schematic from Figure The layout also shows the p-well and n-well over the lower two N-channel transistor levels and the upper P-channel transistor level, respectively.

The development of a conceptual model for an operational transconductance amplifier with Miller compensation has an additional complexity of calculating the feedback capacitance that operates the amplifier in a stable and reliable regime. Figure 18 shows the Excel spreadsheet workout with the evaluation of transistor sizes and dominant pole calculations. Again, the procedure shows the conceptual design strategy mentioned before, the CMOS technology characteristics and specifications flow horizontally to the right and the CMOS design equations, from 5 to 10 , flows downwards illustrating the step-by-by step procedure.

In this case, Figure 18 has two downward decision flows. The first one evaluates the design with the sole calculation of the Miller compensation capacitance to provide the required phase margin and stability criteria [ 3 , 4 , 17 , 27 ]. The second design decision flow determines the size of a transistor to locate a right-hand side pole RHP exactly to cancel the second pole. This way the dominant pole will be extremely alone well inside the gain bandwidth and the amplifier will have, even higher, phase margin PM.

Those capacitances are extremely large and, in this case, the layout generated has a squared shape, like the ones developed with a single straight Excel methodology for capacitors. The Excel methods are used to synthesize the conceptual designs of integrated circuits and devices to teach and develop successful strategies that can be repeated for different CMOS technologies.

Four conceptual design cases are analyzed which are part of a formal course in microelectronics [ 28 ]. The design problems are:. The differential amplifier results are summarized in Table 5. This amplifier stage is shown in Figure 11 and Figure 13 and resolved using the two-dimensional processing method from the Excel methodology illustrated in Figure The results comply with all the specifications established for the conceptual model using the CMOS nm technology as illustrated in Table 5.

Table 6 illustrates the results for the cascode amplifier conceptual model developed using the Excel method shown in Figure Again, this amplifier stage, shown in Figure 15 and Figure 16 , describes the fulfillment of all the specifications established for the conceptual model using the CMOS nm technology. The power dissipation shown for this amplifier includes the three stack of transistors and the bias reference network shown in Figure 15 and Figure The two previous amplifiers, differential, and cascode are not used as independent amplifiers, but they are part of a larger multistage amplifier or microelectronics functional block.

Therefore, the conceptual models for a highly specialized microelectronic device contain 2, 3, or more of those primitive amplifiers described previously. Now we will present results for the conceptual model of a two-stage OTA and of a three-stage operational amplifier.

Table 7 shows results for the conceptual model of a two-stage OTA that includes a differential amplifier and an inverting amplifier that drives the load. This was the amplifier illustrated by Figure 18 and Figure 19 and developed using the methodology of Figure This OTA conceptual design includes additional specifications such as offset voltage, output swing, phase margin, power supply rejection ratio PSRR , gain-bandwidth GB, and settling time.

This is a preview of the project that the students in the microelectronics course develop at the end of the semester. Specifications and measured values from simulation tests in the CMOS cascode amplifier using using 0. Note: Power dissipation includes the bias current for both stages.

Finally, Table 8 illustrates the results obtained from a conceptual design of a 3-stage op-amp using an additional third stage with a shunt feedback scheme to reduce the output resistance of the device. Specifications and measured values from simulation tests in the CMOS 3-stage op-amp using 0. Note: Power dissipation includes the bias current for the three stages. The schematic of the three-stage op-amp conceptual design is shown in Figure The conceptual design developed in this paper shows one of the major steps in designing analog integrated circuits IC for electronic instrumentation devices required by electronics, biomedical, robotics, and computer engineering majors.

In analog IC design, a good combination of function or application with IC technology is necessary to obtain a successful solution. The Excel methodologies are an additional tool to validate and verify the conceptual model required before the device is sent to the foundry facility. Analog IC design consists of three major steps [ 3 ]: electric design, physical design layout , and test design testing.

Engineers and designers must be flexible, use techniques such as the Excel methods, and have a skill set that allows them to simplify and understand a complex conceptual design problem. In microelectronics, device IC design is driven by improving technologies rather than new technologies [ 3 ]. The engineer should be aware that sometimes analog systems applications, where speed, area, or power, have certain advantages over the digital approach.

Even using Excel methods, deep-submicron DSM technologies offer great challenges to the creativity of engineers and designers of IC microelectronic devices. To further increase the potential of using Excel methods in developing instrumentation amplifiers for biomedical applications, we examined a project case study using the methodology to design a 3-stage amplifier having a low voltage and low power operation in the strong inversion zone. This design was going to be used as a subsystem of a bioinstrumentation amplifier required in sensor signal conditioning applications.

The project consisted of the development of a three-element instrumentation amplifier for biomedical applications. Figure 22 illustrates the basic scheme where two op-amps receive the differential mode input signals, and a third op-amp changes the signal from differential mode to single-ended mode referenced to ground. In Figure 22 , each op-amp OA1, OA2, and OA3 must be selected from possible topologies seen in class to achieve certain performance characteristics.

Those op-amps have the following components:. Figure 23 shows a block diagram of each op-amp with all the functional parts of the system. For the power source, the students have the option of developing a high-performance bandgap reference source that is stable with respect to variations in supply voltage, temperature, and noise. The requirements and specifications provided in Table 9 are to be met for each of the op-amp blocks.

Instead of adding a third stage at the output of the two-stage OTA device, they added a second stage differential-amplifier with compensation between the first differential stage and the output stage. This results in improving the frequency response and sacrificing some gain and having a better phase margin for even robust design. Even with this modification, the simulations show an increase in the overall gain compared to the last three stage designs Section 5.

The compensation capacitor Cc and Rz are kept for both differential stages, and the output terminals of both compensation elements are connected all the way to the output of the circuit. The methodology generates the transistor dimensions and capacitor values illustrated in Table 10 and Table Considering the transistor dimensions for this new three stage amplifier design, the first cut expected parameters are calculated as follows, assuming long channel models.

Afterward, the circuit schematic and layout are developed in Electric VLSI to perform simulations tests. The compensation capacitor is designed as a poly-poly2 capacitor. The area for the capacitor is 78 by 78 lambda, with a 47 fF parasitic capacitance.

Figure 24 shows the Excel first cut approximation used for the first part of the conceptual design. Excel methodology for the first part two-stage OTA conceptual design, before connecting the third stage to achieve higher gain and robust conceptual design. The Excel design spreadsheet shown in Figure 24 replicates the strategy which has been proposed in this article.

The CMOS technology characteristics and specifications flow horizontally to the right and the CMOS design equations, from 5 to 10 , Table 1 and Table 2 , flow downwards illustrating the step-by-by step procedure. Figure 25 and Figure 26 illustrate the schematic and layout diagrams for the three-stage amplifier designed using the methodology shown and initiating with the conceptual design equations coming from the long channel model.

The output simulation runs show results that comply with the major specifications required by the design. Figure 27 illustrates the layout frequency sweep where the dB gain, gain bandwidth, and the phase margin are displayed.

The DC gain obtained is Frequency sweep using. Figure 28 shows the time domain simulation to verify the slew rate response. Time domain response using transient analysis in SPICE for the three-stage low-power high-gain op-amp layout. To summarize the complete results for all the theoretical and expected parameters, Table 12 compares:. Comparison of specification, theoretical, schematic and layout results for the three-stage, low-power high-gain operational amplifier conceptual design.

The results compare well to the specified requirements except for the maximum positive swing of the output signal which does not reach the specified value of 1. Furthermore, the power dissipation is slightly higher than anticipated by the theoretical calculations of 0. Some of those specifications could have been obtained with additional calibration and refinements in the final conceptual design.

The student team [ 34 ] decided to compare the conceptual design of this low-power operational amplifier with one that appears in the literature with similar characteristics and is used in similar biomedical applications [ 35 ]. Table 13 shows this comparison where the supply voltage and the power consumption appear higher in our design.

The load capacitance was a specification given by the instructor. Slew rate and bandwidth show a significantly higher performance in our design; however, those were parameters also required by the instructor. The chip area is twice in our design, however, in this case, the instructor did not have any restrictions here and no optimization was performed to reduce the layout artwork whatsoever. Table 13 results, however, illustrate comparisons under different specifications such as the load capacitance and voltage supply.

Some of those conditions were imposed by the course instructor. These changes produced large differences in closed-loop bandwidth and slew rate SR as seen by Table 11 results. Furthermore, the power dissipation and chip area obtained here are twice the values obtained by reference [ 35 ]. Another way to reduce the power dissipation and voltage supply could have been if they have designed the amplifier to operate in the subthreshold zone.

However, the model equations in the Excel method would need to be changed to include the subthreshold model whatsoever. This comparison is an excellent way to encourage confidence in students about the design of integrated circuits at the nanoscale level [ 36 ]. The frequency-domain tests show a DC gain very close to the required for this instrumentation amplifier.

Figure 30 shows the output voltage graph with a measured gain of This gain goes along to up to 10 KH in bandwidth. Finally, a time-domain system test for the instrumentation amplifier was developed to find the maximum output symmetrical swing for the device when amplifying the biomedical sensor signal.

This transient test was performed with a 1. Time domain test for the instrumentation amplifier, where the maximum rail to rail swing is shown. The designed operational amplifier and the instrumentational amplifier have good features for biomedical portable sensor conditioning applications. Selecting an Operational Amplifier and Explanation of Terms. We describe here some typical operational amplifier applications. An inverting amplifier circuit is indicated by a minus sign. A voltage follower is used as a buffer circuit to convert the impedance or to separate circuits.

This is a circuit for amplifying and outputting the difference between two input signals. Here, we will use the ABLIC operational amplifier SA as an example of what items to check in selecting an operational amplifier and explaining operational amplifier attributes.

Check that the power supply voltage is within the range of the operational amplifier operating voltage range. The operational amplifier will work as long as the input signal is within this range. The maximum frequency varies with the factor gain you use to amplify a signal. Make sure that the maximum frequency you want to amplify to is within the range of the factor by which you want to amplify.

The lower this value is, the more you can reduce the power of the system. Normally, an operational amplifier with low current consumption tends to also have low frequency of gain bandwidth. It is an essential attribute affecting the amplification accuracy of operational amplifiers.

Selecting a zero-drift operational amplifier is a highly effective solution for applications that demand high-accuracy signal amplification. Describes zero drift amplifier principle! What is a Zero Drift Amplifier? SA for general use and SA for automotive use operational amplifier provides zero drift operation, wide voltage range 4.

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01 - The Non-Inverting Op-Amp (Amplifier) Circuit

A.2 Operational Amplifier Equivalent Circuit. Analyze, measure and simulate buffer and inverting opamp. Use excel to convert the gain to. tector, and in car alarm systems, the HT is excel- lent for piezo vibratile detector signal amplifier application. Features. · Quad micro power op amp. The voltage gain is set by the two feedback resistors, Ri and Rf. Reference. Fiore, Op Amps and Linear Integrated Circuits. Section , Inverting and Non-.